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| LPC122x 32-bit ARM Cortex-M0 microcontroller; up to 128 kB flash and 8 kB SRAM Rev. 1.1 -- 21 February 2011 Objective data sheet 1. General description The LPC122x extend NXP's 32-bit ARM microcontroller continuum and target a wide range of industrial applications in the areas of factory and home automation. Benefitting from the ARM Cortex-M0 Thumb instruction set, the LPC122x have up to 50 % higher code density compared to common 8/16-bit microcontroller performing typical tasks. The LPC122x also feature an optimized ROM-based divide library for Cortex-M0, which offers several times the arithmetic performance of software-based libraries, as well as highly deterministic cycle time combined with reduced flash code size. The ARM Cortex-M0 efficiency also helps the LPC122x achieve lower average power for similar applications. The LPC122x operate at CPU frequencies of up to 45 MHz.They offer a wide range of flash memory options, from 32 kB to 128 kB. The small 512-byte page erase of the flash memory brings multiple design benefits, such as finer EEPROM emulation, boot-load support from any serial interface and ease of in-field programming with reduced on-chip RAM buffer requirements. The peripheral complement of the LPC122x includes a 10-bit ADC, two comparators with output feedback loop, two UARTs, one SSP/SPI interface, one I2C-bus interface with Fast-mode Plus features, a Windowed Watchdog Timer, a DMA controller, a CRC engine, four general purpose timers, a 32-bit RTC, a 1 % internal oscillator for baud rate generation, and up to 55 General Purpose I/O (GPIO) pins. 2. Features and benefits Processor core ARM Cortex-M0 processor, running at frequencies of up to 45 MHz (one wait state from flash) or 30 MHz (zero wait states from flash). The LPC122x have a high score of over 45 in CoreMark CPU performance benchmark testing, equivalent to 1.51/MHz. ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC). Serial Wire Debug (SWD). System tick timer. Memory Up to 8 kB SRAM. Up to 128 kB on-chip flash programming memory. In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software. Includes ROM-based 32-bit integer division routines. Clock generation unit NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller Crystal oscillator with an operating range of 1 MHz to 25 MHz. 12 MHz Internal RC (IRC) oscillator trimmed to 1 % accuracy that can optionally be used as a system clock. PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the system oscillator or the internal RC oscillator. Clock output function with divider that can reflect the system oscillator clock, IRC clock, main clock, and Watchdog clock. Real-Time Clock (RTC). LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 2 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller Digital peripherals Micro DMA controller with 21 channels. CRC engine. Two UARTs with fractional baud rate generation and internal FIFO. One UART with RS-485 and modem support and one standard UART with IrDA. SSP/SPI controller with FIFO and multi-protocol capabilities. I2C-bus interface supporting full I2C-bus specification and Fast-mode Plus with a data rate of 1 Mbit/s with multiple address recognition and monitor mode. I2C-bus pins have programmable glitch filter. Up to 55 General Purpose I/O (GPIO) pins with programmable pull-up resistor, open-drain mode, programmable digital input glitch filter, and programmable input inverter. Programmable output drive on all GPIO pins. Four pins support high-current output drivers. All GPIO pins can be used as edge and level sensitive interrupt sources. Four general purpose counter/timers with four capture inputs and four match outputs (32-bit timers) or two capture inputs and two match outputs (16-bit timers). Windowed WatchDog Timer (WWDT). Analog peripherals One 8-channel, 10-bit ADC. Two highly flexible analog comparators. Comparator outputs can be programmed to trigger a timer match signal or can be used to emulate 555 timer behavior. Power Three reduced power modes: Sleep, Deep-sleep, and Deep power-down. Processor wake-up from Deep-sleep mode via start logic using 12 port pins. Processor wake-up from Deep-power down and Deep-sleep modes via the RTC. Brownout detect with three separate thresholds each for interrupt and forced reset. Power-On Reset (POR). Integrated PMU (Power Management Unit). Unique device serial number for identification. 3.3 V power supply. Available as 64-pin and 48-pin LQFP package. 3. Applications eMetering Lighting Industrial networking Alarm systems White goods LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 3 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller 4. Ordering information Table 1. Ordering information Package Name Description Version Type number LPC1227FBD64/301 LQFP64 LQFP64: plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2 LPC1226FBD64/301 LQFP64 LQFP64: plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2 LPC1225FBD64/321 LQFP64 LQFP64: plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2 LPC1225FBD64/301 LQFP64 LQFP64: plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2 LPC1224FBD64/121 LQFP64 LQFP64: plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2 LPC1224FBD64/101 LQFP64 LQFP64: plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2 LPC1227FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm LPC1226FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm LPC1225FBD48/321 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm LPC1225FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm LPC1224FBD48/121 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm LPC1224FBD48/101 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm SOT313-2 SOT313-2 SOT313-2 SOT313-2 SOT313-2 SOT313-2 4.1 Ordering options Table 2. Ordering options for LPC122x Flash Total UART SRAM 2 2 2 2 2 2 2 2 2 2 2 2 I2C/ FM+ 1 1 1 1 1 1 1 1 1 1 1 1 SSP/ SPI 1 1 1 1 1 1 1 1 1 1 1 1 ADC GPIO Package channels 8 8 8 8 8 8 8 8 8 8 8 8 55 39 55 39 55 55 39 39 55 55 39 39 LQFP64 LQFP48 LQFP64 LQFP48 LQFP64 LQFP64 LQFP48 LQFP48 LQFP64 LQFP64 LQFP48 LQFP48 Type number LPC1227 LPC1227FBD64/301 128 kB 8 kB LPC1227FBD48/301 128 kB 8 kB LPC1226 LPC1226FBD64/301 96 kB LPC1226FBD48/301 96 kB LPC1225 LPC1225FBD64/321 80 kB LPC1225FBD64/301 64 kB LPC1225FBD48/321 80 kB LPC1225FBD48/301 64 kB LPC1224 LPC1224FBD64/121 48 kB LPC1224FBD64/101 32 kB LPC1224FBD48/121 48 kB LPC1224FBD48/101 32 kB 4 kB 4 kB 4 kB 4 kB 8 kB 8 kB 8 kB 8 kB 8 kB 8 kB LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 4 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller 5. Block diagram SWD XTALIN XTALOUT RESET LPC122x IRC, OSCILLATORS BOD TEST/DEBUG INTERFACE POR CLOCK GENERATION, POWER CONTROL, SYSTEM FUNCTIONS clocks and controls CLKOUT ARM CORTEX-M0 MICRO DMA CONTROLLER system bus master 32/48/64/80/ 96/128 kB FLASH slave 4/8 kB SRAM slave ROM slave AHB-LITE BUS slave GPIO ports HIGH-SPEED GPIO slave AHB-APB BRIDGE slave CRC ENGINE SCK SSEL MISO MOSI RXD0 TXD0 DTR0, DSR0, CTS0, DCD0, RI0, RTS0 RXD1 TXD1 SCL SDA 4 x MAT 4 x CAP 4 x MAT 4 x CAP 2 x MAT 2 x CAP 2 x MAT 2 x CAP SSP/SPI 10-bit ADC AD[7:0] ACMP0_I[3:0] ACMP1_I[3:0] ACMP0_O ACMP1_O VREF_CMP UART0 RS-485 COMPARATOR0/1 UART1 I2C RTC WINDOWED WDT IOCONFIG 32 kHz OSCILLATOR RTCXOUT RTCXIN 32-bit COUNTER/TIMER 0 32-bit COUNTER/TIMER 1 SYSTEM CONTROL 16-bit COUNTER/TIMER 0 16-bit COUNTER/TIMER 1 MICRO DMA REGISTERS Grey-shaded blocks represent peripherals with connection to the micro DMA 002aaf269 Fig 1. LPC122x block diagram LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 5 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller 6. Pinning information 6.1 Pinning 51 PIO1_3/WAKEUP 58 RTCXOUT 56 VDD(3V3) 55 VSS XTALIN XTALOUT VREF_CMP PIO0_19 PIO0_20 PIO0_21 PIO0_22 PIO0_23 PIO0_24 1 2 3 4 5 6 7 8 9 49 R/PIO1_1 48 R/PIO1_0 47 R/PIO0_31 46 R/PIO0_30 45 PIO0_18 44 PIO0_17 43 PIO0_16 42 PIO0_15 41 PIO0_14 40 RESET/PIO0_13 39 PIO0_12(1) 38 PIO0_11 37 PIO0_10 36 PIO2_7 35 PIO2_6 34 PIO2_5 33 PIO2_4 PIO2_3 32 002aaf554 62 PIO2_11 61 PIO2_10 64 VSSIO 63 VDD(IO) 57 RTCXIN 54 PIO1_6 53 PIO1_5 52 PIO1_4 PIO2_0 29 LPC122x SWDIO/PIO0_25 10 SWCLK/PIO0_26 11 PIO0_27(1) 12 PIO2_12 13 PIO2_13 14 PIO2_14 15 PIO2_15 16 PIO0_29(1) 18 PIO0_0 19 PIO0_1 20 PIO0_2 21 PIO0_3 22 PIO0_4 23 PIO0_5 24 PIO0_6 25 PIO0_7 26 PIO0_8 27 PIO0_9 28 PIO2_1 30 PIO0_28(1) 17 PIO2_2 31 (1) High-current output driver. Remark: For a full listing of all functions for each pin see Table 3. Fig 2. Pin configuration LQFP64 package LPC122X All information provided in this document is subject to legal disclaimers. 50 PIO1_2 60 PIO2_9 59 PIO2_8 (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 6 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller 39 PIO1_3/WAKEUP 45 RTCXOUT XTALIN XTALOUT VREF_CMP PIO0_19 PIO0_20 PIO0_21 PIO0_22 PIO0_23 PIO0_24 1 2 3 4 5 6 7 8 9 37 R/PIO1_1 36 R/PIO1_0 35 R/PIO0_31 34 R/PIO0_30 33 PIO0_18 32 PIO0_17 31 PIO0_16 30 PIO0_15 29 PIO0_14 28 RESET/PIO0_13 27 PIO0_12(1) 26 PIO0_11 25 PIO0_10 PIO0_9 24 002aaf724 44 VDD(3V3) 46 RTCXIN 42 PIO1_6 41 PIO1_5 40 PIO1_4 PIO0_6 21 LPC122x SWDIO/PIO0_25 10 SWCLK/PIO0_26 11 PIO0_27(1) 12 PIO0_28(1) 13 PIO0_29(1) 14 PIO0_0 15 PIO0_1 16 PIO0_2 17 PIO0_3 18 PIO0_4 19 PIO0_5 20 PIO0_7 22 PIO0_8 23 (1) High-current output driver. Remark: For a full listing of all functions for each pin see Table 3. Fig 3. Pin configuration LQFP48 package LPC122X All information provided in this document is subject to legal disclaimers. 38 PIO1_2 47 VDD(IO) 48 VSSIO 43 VSS (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 7 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller 6.2 Pin description All pins except the supply pins can have more than one function as shown in Table 3. The pin function is selected through the pin's IOCON register in the IOCONFIG block. The multiplexed functions (see Table 4) include the counter/timer inputs and outputs, the UART receive, transmit, and control functions, and the serial wire debug functions. For each pin, the default function is listed first together with the pin's reset state. Table 3. Symbol LPC122x pin description Pin LQFP48 Pin LQFP64 Start Type Reset Description logic state [1] input PIO0_0 to PIO0_31 I/O Port 0 -- Port 0 is a 32-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block. I; PU I; PU I; PU I; PU I; PU I; PU I; PU PIO0_0 -- General purpose digital input/output pin. RTS0 -- Request To Send output for UART0. PIO0_1 -- General purpose digital input/output pin. RXD0 -- Receiver input for UART0. CT32B0_CAP0 -- Capture input, channel 0 for 32-bit timer 0. CT32B0_MAT0 -- Match output, channel 0 for 32-bit timer 0. PIO0_2 -- General purpose digital input/output pin. TXD0 -- Transmitter output for UART0. CT32B0_CAP1 -- Capture input, channel 1 for 32-bit timer 0. CT32B0_MAT1 -- Match output, channel 1 for 32-bit timer 0. PIO0_3 -- General purpose digital input/output pin. DTR0 -- Data Terminal Ready output for UART0. CT32B0_CAP2 -- Capture input, channel 2 for 32-bit timer 0. CT32B0_MAT2 -- Match output, channel 2 for 32-bit timer 0. PIO0_4 -- General purpose digital input/output pin. DSR0 -- Data Set Ready input for UART0. CT32B0_CAP3 -- Capture input, channel 3 for 32-bit timer 0. CT32B0_MAT3 -- Match output, channel 3 for 32-bit timer 0. PIO0_5 -- General purpose digital input/output pin. DCD0 -- Data Carrier Detect input for UART0. PIO0_6 -- General purpose digital input/output pin. RI0 -- Ring Indicator input for UART0. CT32B1_CAP0 -- Capture input, channel 0 for 32-bit timer 1. CT32B1_MAT0 -- Match output, channel 0 for 32-bit timer 1. PIO0_0/RTS0 PIO0_1/RXD0/ CT32B0_CAP0/ CT32B0_MAT0 15 19 16 20 [2] yes yes I/O O I/O I I O [2] PIO0_2/TXD0/ CT32B0_CAP1/ CT32B0_MAT1 17 21 [2] yes I/O O I O PIO0_3/DTR0/ CT32B0_CAP2/ CT32B0_MAT2 18 22 [2] yes I/O O I O PIO0_4/DSR0/ CT32B0_CAP3/ CT32B0_MAT3 19 23 [2] yes I/O I I O PIO0_5/DCD0 PIO0_6/RI0/ CT32B1_CAP0/ CT32B1_MAT0 20 24 21 25 [2] yes yes I/O I I/O I I O [2] LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 8 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller Table 3. Symbol LPC122x pin description ...continued Pin LQFP48 Pin LQFP64 Start Type Reset Description logic state [1] input PIO0_7/CTS0/ CT32B1_CAP1/ CT32B1_MAT1 22 26 [2] yes I/O I I O I; PU I; PU I; PU I; IA I; IA I; PU PIO0_7 -- General purpose digital input/output pin. CTS0 -- Clear To Send input for UART0. CT32B1_CAP1 -- Capture input, channel 1 for 32-bit timer 1. CT32B1_MAT1 -- Match output, channel 1 for 32-bit timer 1. PIO0_8 -- General purpose digital input/output pin. RXD1 -- Receiver input for UART1. CT32B1_CAP2 -- Capture input, channel 2 for 32-bit timer 1. CT32B1_MAT2 -- Match output, channel 2 for 32-bit timer 1. PIO0_9 -- General purpose digital input/output pin. TXD1 -- Transmitter output for UART1. CT32B1_CAP3 -- Capture input, channel 3 for 32-bit timer 1. CT32B1_MAT3 -- Match output, channel 3 for 32-bit timer 1. PIO0_10 -- General purpose digital input/output pin. SCL -- I2C-bus clock input/output. PIO0_11 -- General purpose digital input/output pin. SDA -- I2C-bus data input/output. CT16B0_CAP0 -- Capture input, channel 0 for 16-bit timer 0. CT16B0_MAT0 -- Match output, channel 0 for 16-bit timer 0. PIO0_12 -- General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler. High-current output driver. CLKOUT -- Clock out pin. CT16B0_CAP1 -- Capture input, channel 1 for 16-bit timer 0. CT16B0_MAT1 -- Match output, channel 1 for 16-bit timer 0. RESET -- External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. PIO0_13 -- General purpose digital input/output pin. PIO0_14 -- General purpose digital input/output pin. SCK -- Serial clock for SSP/SPI. PIO0_15 -- General purpose digital input/output pin. SSEL -- Slave select for SSP/SPI. CT16B1_CAP0 -- Capture input, channel 0 for 16-bit timer 1. CT16B1_MAT0 -- Match output, channel 0 for 16-bit timer 1. PIO0_16 -- General purpose digital input/output pin. MISO -- Master In Slave Out for SSP/SPI. CT16B1_CAP1 -- Capture input, channel 1 for 16-bit timer 1. CT16B1_MAT1 -- Match output, channel 1 for 16-bit timer 1. PIO0_8/RXD1/ CT32B1_CAP2/ CT32B1_MAT2 23 27 [2] yes I/O I I O PIO0_9/TXD1/ CT32B1_CAP3/ CT32B1_MAT3 24 28 [2] yes I/O O I O PIO0_10/SCL PIO0_11/SDA/ CT16B0_CAP0/ CT16B0_MAT0 25 37 26 38 [3] yes yes I/O I/O I/O I/O I O [3] PIO0_12/CLKOUT/ CT16B0_CAP1/ CT16B0_MAT1 27 39 [7] no I/O O I O RESET/PIO0_13 28 40 [4] I; PU no I I/O PIO0_14/SCK PIO0_15/SSEL/ CT16B1_CAP0/ CT16B1_MAT0 29 41 30 42 [2] I; PU I; PU I; PU - no no I/O I/O I/O I/O I O [2] PIO0_16/MISO/ CT16B1_CAP1/ CT16B1_MAT1 31 43 [2] no I/O I/O I O LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 9 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller Table 3. Symbol LPC122x pin description ...continued Pin LQFP48 Pin LQFP64 Start Type Reset Description logic state [1] input PIO0_17/MOSI PIO0_18/SWCLK/ CT32B0_CAP0/ CT32B0_MAT0 32 44 33 45 [2] no no I/O I/O I/O I I O I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU - PIO0_17 -- General purpose digital input/output pin. MOSI -- Master Out Slave In for SSP/SPI. PIO0_18 -- General purpose digital input/output pin. SWCLK -- Serial wire clock, alternate location. CT32B0_CAP0 -- Capture input, channel 0 for 32-bit timer 0. CT32B0_MAT0 -- Match output, channel 0 for 32-bit timer 0. PIO0_19 -- General purpose digital input/output pin. ACMP0_I0 -- Input 0 for comparator 0. CT32B0_CAP1 -- Capture input, channel 1 for 32-bit timer 0. CT32B0_MAT1 -- Match output, channel 1 for 32-bit timer 0 PIO0_20 -- General purpose digital input/output pin. ACMP0_I1 -- Input 1 for comparator 0. CT32B0_CAP2 -- Capture input, channel 2 for 32-bit timer 0. CT32B0_MAT2 -- Match output, channel 2 for 32-bit timer 0. PIO0_21 -- General purpose digital input/output pin. ACMP0_I2 -- Input 2 for comparator 0. CT32B0_CAP3 -- Capture input, channel 3 for 32-bit timer 0. CT32B0_MAT3 -- Match output, channel 3 for 32-bit timer 0. PIO0_22 -- General purpose digital input/output pin. ACMP0_I3 -- Input 3 for comparator 0. PIO0_23 -- General purpose digital input/output pin. ACMP1_I0 -- Input 0 for comparator 1. CT32B1_CAP0 -- Capture input, channel 0 for 32-bit timer 1. CT32B1_MAT0 -- Match output, channel 0 for 32-bit timer 1. PIO0_24 -- General purpose digital input/output pin. ACMP1_I1 -- Input 1 for comparator 1. CT32B1_CAP1 -- Capture input, channel 1 for 32-bit timer 1. CT32B1_MAT1 -- Match output, channel 1 for 32-bit timer 1. SWDIO -- Serial wire debug input/output, default location. ACMP1_I2 -- Input 2 for comparator 1. CT32B1_CAP2 -- Capture input, channel 2 for 32-bit timer 1. CT32B1_MAT2 -- Match output, channel 2 for 32-bit timer 1. PIO0_25 -- General purpose digital input/output pin. SWCLK -- Serial wire clock, default location. ACMP1_I3 -- Input 3 for comparator 1. CT32B1_CAP3 -- Capture input, channel 3 or 32-bit timer 1. CT32B1_MAT3 -- Match output, channel 3 for 32-bit timer 1. PIO0_26 -- General purpose digital input/output pin. (c) NXP B.V. 2011. All rights reserved. [2] PIO0_19/ACMP0_I0/ CT32B0_CAP1/ CT32B0_MAT1 4 4 [5] no I/O I I O PIO0_20/ACMP0_I1/ CT32B0_CAP2/ CT32B0_MAT2 5 5 [5] no I/O I I O PIO0_21/ACMP0_I2/ CT32B0_CAP3/ CT32B0_MAT3 6 6 [5] no I/O I I O PIO0_22/ACMP0_I3 PIO0_23/ ACMP1_I0/ CT32B1_CAP0/ CT32B1_MAT0 PIO0_24/ACMP1_I1/ CT32B1_CAP1/ CT32B1_MAT1 7 8 7 8 [5] no no I/O I I/O I I O [5] 9 9 [5] no I/O I I O SWDIO/ACMP1_I2/ CT32B1_CAP2/ CT32B1_MAT2/ PIO0_25 10 10 [5] no I/O I I O I/O SWCLK/ACMP1_I3/ CT32B1_CAP3/ CT32B1_MAT3/ PIO0_26 11 11 [5] no I I I O I/O LPC122X All information provided in this document is subject to legal disclaimers. Objective data sheet Rev. 1.1 -- 21 February 2011 10 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller Table 3. Symbol LPC122x pin description ...continued Pin LQFP48 Pin LQFP64 Start Type Reset Description logic state [1] input PIO0_27/ACMP0_O 12 12 [7] no I/O O I; PU I; PU I; PU I; PU I; PU - PIO0_27 -- General purpose digital input/output pin (high-current output driver). ACMP0_O -- Output for comparator 0. PIO0_28 -- General purpose digital input/output pin (high-current output driver). ACMP1_O -- Output for comparator 1. CT16B0_CAP0 -- Capture input, channel 0 for 16-bit timer 0. CT16B0_MAT0 -- Match output, channel 0 for 16-bit timer 0. PIO0_29 -- General purpose digital input/output pin (high-current output driver). ROSC -- Relaxation oscillator for 555 timer applications. CT16B0_CAP1 -- Capture input, channel 1 for 16-bit timer 0. CT16B0_MAT1 -- Match output, channel 1 for 16-bit timer 0. R -- Reserved. Configure for an alternate function in the IOCONFIG block. PIO0_30 -- General purpose digital input/output pin. AD0 -- A/D converter, input 0. R -- Reserved. Configure for an alternate function in the IOCONFIG block. PIO0_31 -- General purpose digital input/output pin. AD1 -- A/D converter, input 1. Port 1 -- Port 1 is a 32-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block. Pins PIO1_7 through PIO1_31 are not available. PIO0_28/ACMP1_O/ CT16B0_CAP0/ CT16B0_MAT0 13 17 [7] no I/O O I O PIO0_29/ROSC/ CT16B0_CAP1/ CT16B0_MAT1 14 18 [7] no I/O I/O I O R/PIO0_30/AD0 34 46 [5] no I I/O I R/PIO0_31/AD1 35 47 [5] no I I/O I PIO1_0 to PIO1_6 I/O R/PIO1_0/AD2 36 48 [5] no O I/O I I; PU I; PU I; PU I; PU I; PU - R -- Reserved. Configure for an alternate function in the IOCONFIG block. PIO1_0 -- General purpose digital input/output pin. AD2 -- A/D converter, input 2. R -- Reserved. Configure for an alternate function in the IOCONFIG block. PIO1_1 -- General purpose digital input/output pin. AD3 -- A/D converter, input 3. PIO1_2 -- General purpose digital input/output pin. SWDIO -- Serial wire debug input/output, alternate location. AD4 -- A/D converter, input 4. PIO1_3 -- General purpose digital input/output pin. AD5 -- A/D converter, input 5. WAKEUP -- Deep power-down mode wake-up pin. PIO1_4 -- General purpose digital input/output pin. AD6 -- A/D converter, input 6. (c) NXP B.V. 2011. All rights reserved. R/PIO1_1/AD3 37 49 [5] no I I/O I PIO1_2/SWDIO/AD4 38 50 [5] no I/O I/O I PIO1_3/AD5/WAKEUP 39 51 [6] no I/O I I PIO1_4/AD6 40 52 [5] no I/O I LPC122X All information provided in this document is subject to legal disclaimers. Objective data sheet Rev. 1.1 -- 21 February 2011 11 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller Table 3. Symbol LPC122x pin description ...continued Pin LQFP48 Pin LQFP64 Start Type Reset Description logic state [1] input PIO1_5/AD7/ CT16B1_CAP0/ CT16B1_MAT0 41 53 [5] no I/O I I O I; PU I; PU - PIO1_5 -- General purpose digital input/output pin. AD7 -- A/D converter, input 7. CT16B1_CAP0 -- Capture input, channel 0 for 16-bit timer 1. CT16B1_MAT0 -- Match output, channel 0 for 16-bit timer 1. PIO1_6 -- General purpose digital input/output pin. CT16B1_CAP1 -- Capture input, channel 1 for 16-bit timer 1. CT16B1_MAT1 -- Match output, channel 1 for 16-bit timer 1. Port 2 -- Port 2 is a 32-bit I/O port with individual direction and function controls for each bit. The operation of port 2 pins depends on the function selected through the IOCONFIG register block. Pins PIO2_16 through PIO2_31 are not available. PIO1_6/ CT16B1_CAP1/ CT16B1_MAT1 PIO2_0 to PIO2_15 42 54 [2] no I/O I O I/O PIO2_0/ CT16B0_CAP0/ CT16B0_MAT0/ RTS0 PIO2_1/ CT16B0_CAP1/ CT16B0_MAT1/RXD0 - 29 [2] no I/O I O O I; PU I; PU I; PU I; PU I; PU I; PU - PIO2_0 -- General purpose digital input/output pin. CT16B0_CAP0 -- Capture input, channel 0 for 16-bit timer 0. CT16B0_MAT0 -- Match output, channel 0 for 16-bit timer 0. RTS0 -- Request To Send output for UART0. PIO2_1 -- General purpose digital input/output pin. CT16B0_CAP1 -- Capture input, channel 1 for 16-bit timer 0. CT16B0_MAT1 -- Match output, channel 1 for 16-bit timer 0. RXD0 -- Receiver input for UART0. PIO2_2 -- General purpose digital input/output pin. CT16B1_CAP0 -- Capture input, channel 0 for 16-bit timer 1. CT16B1_MAT0 -- Match output, channel 0 for 16-bit timer 1. TXD0 -- Transmitter output for UART0. PIO2_3 -- General purpose digital input/output pin. CT16B1_CAP1 -- Capture input, channel 1 for 16-bit timer 1. CT16B1_MAT1 -- Match output, channel 1 for 16-bit timer 1. DTR0 -- Data Terminal Ready output for UART0. PIO2_4 -- General purpose digital input/output pin. CT32B0_CAP0 -- Capture input, channel 0 for 32-bit timer 0. CT32B0_MAT0 -- Match output, channel 0 for 32-bit timer 0. CTS0 -- Clear To Send input for UART0. PIO2_5 -- General purpose digital input/output pin. CT32B0_CAP1 -- Capture input, channel 1 for 32-bit timer 0. CT32B0_MAT1 -- Match output, channel 1 for 32-bit timer 0. RI0 -- Ring Indicator input for UART0. - 30 [2] no I/O I O I PIO2_2/ CT16B1_CAP0/ CT16B1_MAT0/TXD0 - 31 [2] no I/O I O O PIO2_3/ CT16B1_CAP1/ CT16B1_MAT1/DTR0 - 32 [2] no I/O I O O PIO2_4/ CT32B0_CAP0/ CT32B0_MAT0/CTS0 - 33 [2] no I/O I O I PIO2_5/ CT32B0_CAP1/ CT32B0_MAT1/RI0 - 34 [2] no I/O I O I LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 12 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller Table 3. Symbol LPC122x pin description ...continued Pin LQFP48 Pin LQFP64 Start Type Reset Description logic state [1] input PIO2_6/ CT32B0_CAP2/ CT32B0_MAT2/DCD0 - 35 [2] no I/O I O I I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU I; PU - PIO2_6 -- General purpose digital input/output pin. CT32B0_CAP2 -- Capture input, channel 2 for 32-bit timer 0. CT32B0_MAT2 -- Match output, channel 2 for 32-bit timer 0. DCD0 -- Data Carrier Detect input for UART0. PIO2_7 -- General purpose digital input/output pin. CT32B0_CAP3 -- Capture input, channel 3 for 32-bit timer 0. CT32B0_MAT3 -- Match output, channel 3 for 32-bit timer 0. DSR0 -- Data Set Ready input for UART0. PIO2_8 -- General purpose digital input/output pin. CT32B1_CAP0 -- Capture input, channel 0 for 32-bit timer 1. CT32B1_MAT0 -- Match output, channel 0 for 32-bit timer 1. PIO2_9 -- General purpose digital input/output pin. CT32B1_CAP1 -- Capture input, channel 1 for 32-bit timer 1. CT32B1_MAT1 -- Match output, channel 1 for 32-bit timer 1. PIO2_10 -- General purpose digital input/output pin. CT32B1_CAP2 -- Capture input, channel 2 for 32-bit timer 1. CT32B1_MAT2 -- Match output, channel 2 for 32-bit timer 1. TXD1 -- Transmitter output for UART1. PIO2_11 -- General purpose digital input/output pin. CT32B1_CAP3 -- Capture input, channel 3 for 32-bit timer 1. CT32B1_MAT3 -- Match output, channel 3 for 32-bit timer 1. RXD1 -- Receiver input for UART1. PIO2_12 -- General purpose digital input/output pin. RXD1 -- Receiver input for UART1. PIO2_13 -- General purpose digital input/output pin. TXD1 -- Transmitter output for UART1. PIO2_14 -- General purpose digital input/output pin. PIO2_15 -- General purpose digital input/output pin. Input to the 32 kHz oscillator circuit. Output from the 32 kHz oscillator amplifier. Input to the system oscillator circuit and internal clock generator circuits. Output from the system oscillator amplifier. Reference voltage for comparator. PIO2_7/ CT32B0_CAP3/ CT32B0_MAT3/DSR0 - 36 [2] no I/O I O I PIO2_8/ CT32B1_CAP0/ CT32B1_MAT0 PIO2_9/ CT32B1_CAP1/ CT32B1_MAT1 PIO2_10/ CT32B1_CAP2/ CT32B1_MAT2/TXD1 - 59 [2] no I/O I O - 60 [2] no I/O I O - 61 [2] no I/O I O O PIO2_11/ CT32B1_CAP3/ CT32B1_MAT3/RXD1 - 62 [2] no I/O I O I PIO2_12/RXD1 PIO2_13/TXD1 PIO2_14 PIO2_15 RTCXIN RTCXOUT XTALIN XTALOUT VREF_CMP - 13 14 15 16 [2] no no no no - I/O I I/O O I/O I/O I O I O I [2] [2] [2] 46 57 45 58 1 2 3 1 2 3 LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 13 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller Table 3. Symbol LPC122x pin description ...continued Pin LQFP48 Pin LQFP64 Start Type Reset Description logic state [1] input VDD(IO) VDD(3V3) VSSIO VSS [1] [2] [3] [4] [5] [6] [7] 47 63 44 56 48 64 43 55 - I I I I - Input/output supply voltage. 3.3 V supply voltage to the internal regulator and the ADC. Also used as the ADC reference voltage. Ground. Ground. Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled. 3.3 V tolerant, digital I/O pin; default: pull-up enabled, no hysteresis. I2C-bus pins; 5 V tolerant; open-drain; default: no pull-up/pull-down; no hysteresis. 3.3 V tolerant, digital I/O pin with RESET function; default: pull-up enabled, no hysteresis. An external pull-up resistor is required on this pin for the Deep power-down mode. 3.3 V tolerant, digital I/O pin with analog function; default: pull-up enabled, no hysteresis. 3.3 V tolerant, digital I/O pin with analog function and WAKEUP function; default: pull-up enabled, no hysteresis. 3.3 V tolerant, high-drive digital I/O pin; default: pull-up enabled, no hysteresis. To enable a peripheral function, find the corresponding port pin, or select a port pin if the function is multiplexed, and program the port pin's IOCONFIG register to enable that function. The primary SWD functions and RESET are the default functions on their pins after reset, all other digital pins default to GPIO. Table 4. Peripheral Analog comparators Pin multiplexing Function ROSC ACMP0_I0 ACMP0_I1 ACMP0_I2 ACMP0_I3 ACMP0_O ACMP1_I0 ACMP1_I1 ACMP1_I2 ACMP1_I3 ACMP1_O ADC AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 Type I/O I I I I O I I I I O I I I I I I I I Available on ports: PIO0_29 PIO0_19 PIO0_20 PIO0_21 PIO0_22 PIO0_27 PIO0_23 PIO0_24 PIO0_25 PIO0_26 PIO0_28 PIO0_30 PIO0_31 PIO1_0 PIO1_1 PIO1_2 PIO1_3 PIO1_4 PIO1_5 - LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 14 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller Pin multiplexing Function CT16B0_CAP0 CT16B0_CAP1 CT16B0_MAT0 CT16B0_MAT1 Type I I O O I I O O I I I I O O O O I I I I O O O O I O I I I O I O I O I/O I/O I/O I/O I/O I/O Available on ports: PIO0_11 PIO0_12 PIO0_11 PIO0_12 PIO0_15 PIO0_16 PIO0_15 PIO0_16 PIO0_1 PIO0_2 PIO0_3 PIO0_4 PIO0_1 PIO0_2 PIO0_3 PIO0_4 PIO0_6 PIO0_7 PIO0_8 PIO0_9 PIO0_6 PIO0_7 PIO0_8 PIO0_9 PIO0_1 PIO0_2 PIO0_7 PIO0_5 PIO0_4 PIO0_3 PIO0_6 PIO0_0 PIO0_8 PIO0_9 PIO0_14 PIO0_16 PIO0_17 PIO0_15 PIO0_10 PIO0_11 PIO0_28 PIO0_29 PIO0_28 PIO0_29 PIO1_5 PIO1_6 PIO1_5 PIO1_6 PIO0_18 PIO0_19 PIO0_20 PIO0_21 PIO0_18 PIO0_19 PIO0_20 PIO0_21 PIO0_23 PIO0_24 PIO0_25 PIO0_26 PIO0_23 PIO0_24 PIO0_25 PIO0_26 PIO2_1 PIO2_2 PIO2_4 PIO2_6 PIO2_7 PIO2_3 PIO2_5 PIO2_0 PIO2_11 PIO2_10 PIO2_0 PIO2_1 PIO2_0 PIO2_1 PIO2_2 PIO2_3 PIO2_2 PIO2_3 PIO2_4 PIO2_5 PIO2_6 PIO2_7 PIO2_4 PIO2_5 PIO2_6 PIO2_7 PIO2_8 PIO2_9 PIO2_10 PIO2_11 PIO2_8 PIO2_9 PIO2_10 PIO2_11 PIO2_12 PIO2_13 - Table 4. Peripheral CT16B0 CT16B1 CT16B1_CAP0 CT16B1_CAP1 CT16B1_MAT0 CT16B1_MAT1 CT32B0 CT32B0_CAP0 CT32B0_CAP1 CT32B0_CAP2 CT32B0_CAP3 CT32B0_MAT0 CT32B0_MAT1 CT32B0_MAT2 CT32B0_MAT3 CT32B1 CT32B1_CAP0 CT32B1_CAP1 CT32B1_CAP2 CT32B1_CAP3 CT32B1_MAT0 CT32B1_MAT1 CT32B1_MAT2 CT32B1_MAT3 UART0 RXD0 TXD0 CTS0 DCD0 DSR0 DTR0 RI0 RTS0 UART1 SSP/SPI RXD1 TXD1 SCK MISO MOSI SSEL I2C SCL SDA LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 15 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller Pin multiplexing Function SWCLK[1] SWDIO[1] RESET CLKOUT Type I I/O I O Available on ports: PIO0_18 PIO0_25 PIO0_13 PIO0_12 PIO0_26 PIO1_2 - Table 4. Peripheral SWD Reset Clockout pin [1] After reset, the SWD functions are selected by default on pins PIO0_26 and PIO0_25. 7. Functional description 7.1 ARM Cortex-M0 processor The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. 7.1.1 System tick timer The ARM Cortex-M0 includes a System Tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception at a 10 ms interval. 7.2 On-chip flash program memory The LPC122x contain up to 128 kB of on-chip flash memory. 7.3 On-chip SRAM The LPC122x contain a total of up to 8 kB on-chip static RAM memory. 7.4 Memory map The LPC122x incorporates several distinct memory regions, shown in the following figures. Figure 4 shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping. The AHB peripheral area is 2 megabyte in size, and is divided to allow for up to 128 peripherals. The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals. Each peripheral of either type is allocated 16 kilobytes of space. This allows simplifying the address decoding for each peripheral. LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 16 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller AHB peripherals 0x5008 0000 4 GB LPC122x 0xFFFF FFFF reserved 0xE010 0000 private peripheral bus reserved 0x5008 0000 AHB peripherals 0x5000 0000 7 CRC 3 - 6 reserved 0x5007 0000 0x5003 0000 2 GPIO PIO2 GPIO PIO1 GPIO PIO0 APB peripherals 0x5002 0000 0x5001 0000 0x5000 0000 0x4008 0000 1 0 0xE000 0000 reserved 22 - 31 reserved 0x4008 0000 1 GB APB peripherals 0x4000 0000 21 20 reserved 0x1FFF 2000 8 kB boot ROM reserved 8 kB custom ROM reserved 16 kB NXP library ROM reserved 0x1000 2000 8 kB SRAM (LPC1225/6/7) 4 kB SRAM (LPC1224) reserved 0x0002 0000 128 kB on-chip flash (LPC1227/301) 96 kB on-chip flash (LPC1226/301) 80 kB on-chip flash (LPC1225/321) 64 kB on-chip flash (LPC1225/301) 48 kB on-chip flash (LPC1224/121) 0 GB 32 kB on-chip flash (LPC1224/101) 0x0001 8000 0x0001 4000 0x0001 0000 0x0000 C000 0x0000 8000 0x0000 0000 0x0000 00C0 active interrupt vectors 0x0000 0000 0x1000 1000 0x1000 0000 0x1FFF 0000 0x1FFE 2000 0x1FFE 0000 0x1FFC 4000 9 - 13 reserved 0x1FFC 0000 8 7 6 5 4 3 2 1 0 ADC 32-bit counter/timer 1 32-bit counter/timer 0 16-bit counter/timer 1 16-bit counter/timer 0 UART1 UART0 WDT I2C-bus 19 18 17 16 15 14 comparator 0/1 RTC micro DMA registers system control IOCONFIG SSP reserved PMU 0x4005 8000 0x4005 4000 0x4005 0000 0x4004 C000 0x4004 8000 0x4004 4000 0x4004 0000 0x4003 C000 0x4003 8000 0x4002 4000 0x4002 0000 0x4001 C000 0x4001 8000 0x4001 4000 0x4001 0000 0x4000 C000 0x4000 8000 0x4000 4000 0x4000 0000 002aaf270 Fig 4. LPC122x memory map 7.5 Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 7.5.1 Features * Controls system exceptions and peripheral interrupts. LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 17 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller * In the LPC122x, the NVIC supports 32 vectored interrupts. In addition, up to 12 of the individual GPIO inputs are NVIC-vector capable. * Four programmable interrupt priority levels with hardware priority level masking. * Software interrupt generation. * Non-maskable Interrupt (NMI) can be programmed to use any of the peripheral interrupts. The NMI is not available on an external pin. 7.5.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. Any GPIO pin (total of up to 55 pins) regardless of the selected function, can be programmed to generate an interrupt on a level, a rising edge or falling edge, or both. 7.6 IOCONFIG block The IOCONFIG block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. 7.6.1 Features * * * * * Programmable pull-up resistor. Programmable digital glitch filter. Programmable input inverter. Programmable drive current. Programmable open-drain mode. 7.7 Micro DMA controller The micro DMA controller enables memory-to-memory, memory-to-peripheral, and peripheral-to-memory data transfers. The supported peripherals are: UART0 (transmit and receive), UART1 (transmit and receive), SSP/SPI (transmit and receive), ADC, RTC, 32-bit counter/timer 0 (match output channels 0 and 1), 32-bit counter/timer 1 (match output channels 0 and 1), 16-bit counter/timer 0 (match output channel 0), 16-bit counter/timer 1 (match output channel 0), comparator 0, comparator 1, GPIO0 to GPIO2. 7.7.1 Features * Single AHB-Lite master for transferring data using a 32-bit address bus and 32-bit data bus. * 21 DMA channels. * Handshake signals and priority level programmable for each channel. * Each priority level arbitrates using a fixed priority that is determined by the DMA channel number. LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 18 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller * Supports memory-to-memory, memory-to-peripheral, and peripheral-to-memory transfers. * Supports multiple DMA cycle types and multiple DMA transfer widths. * Performs all DMA transfers using the single AHB-Lite burst type. 7.8 CRC engine The Cyclic Redundancy Check (CRC) engine with programmable polynomial settings supports several CRC standards commonly used. To save system power and bus bandwidth, the CRC engine supports DMA transfers. 7.8.1 Features * Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32. - CRC-CCITT: x16 + x12 + x5 + 1 - CRC-16: x16 + x15 + x2 + 1 - CRC-32: x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1 * Bit order reverse and 1's complement programmable setting for input data and CRC sum. * Programmable seed number setting. * Supports CPU programmed I/O or DMA back-to-back transfer. * Accept any size of data width per write: 8, 16 or 32-bit. - 8-bit write: 1-cycle operation - 16-bit write: 2-cycle operation (8-bit 2-cycle) - 32-bit write: 4-cycle operation (8-bit 4-cycle) 7.9 Fast general purpose parallel I/O Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back as well as the current state of the port pins. 7.9.1 Features * Bit level set and clear registers allow a single instruction to set or clear any number of bits in one port. * Direction control of individual bits. * All I/O default to inputs after reset. 7.10 UARTs The LPC122x contains two UARTs. UART0 supports full modem control and RS-485/9-bit mode and allows both software address detection and automatic hardware address detection using 9-bit mode. The UARTs include a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 19 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller 7.10.1 Features * * * * 16-byte Receive and Transmit FIFOs. Register locations conform to 16C550 industry standard. Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B. Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. control implementation. * Auto-baud capabilities and FIFO control mechanism that enables software flow * Support for RS-485/9-bit mode (UART0). * Support for modem control (UART0). 7.11 SSP/SPI serial I/O controller The LPC122x contain one SSP/SPI controller. The SSP/SPI controller is capable of operation on a SSP, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. 7.11.1 Features * Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National Semiconductor Microwire buses * * * * Synchronous serial communication Master or slave operation 8-frame FIFOs for both transmit and receive 4-bit to 16-bit frame 7.12 I2C-bus serial I/O controller The LPC122x contain one I2C-bus controller. The I2C-bus is bidirectional for inter-IC control using only two wires: a serial clock line (SCL) and a serial data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be controlled by more than one bus master connected to it. 7.12.1 Features * The I2C-interface is a standard I2C-compliant bus interface with open-drain pins and supports I2C Fast-mode Plus with bit rates of up to 1 Mbit/s. * Programmable digital glitch filter providing a 60 ns to 1 s input filter. * Easy to configure as master, slave, or master/slave. * Programmable clocks allow versatile rate control. LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 20 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller * Bidirectional data transfer between masters and slaves. * Multi-master bus (no central master). * Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. * Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. * Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. * The I2C-bus can be used for test and diagnostic purposes. * The I2C-bus controller supports multiple address recognition and a bus monitor mode. 7.13 10-bit ADC The LPC122x contains one ADC. It is a single 10-bit successive approximation ADC with eight channels. 7.13.1 Features * * * * * * * * 10-bit successive approximation ADC. Input multiplexing among 8 pins. Power-down mode. Measurement range 0 V to VDD(3V3). 10-bit conversion time of 257 kHz. Burst conversion mode for single or multiple inputs. Optional conversion on transition of input pin or counter/timer match signal. Individual result registers for each ADC channel to reduce interrupt overhead. 7.14 Comparator block The comparator block consists of two analog comparators. 7.14.1 Features * Up to six selectable external sources per comparator; fully configurable on either positive or negative comparator input channels. * BOD 0.9 V internal reference voltage selectable on both comparators; configurable on either positive or negative comparator input channels. * 32-stage Voltage Ladder internal reference voltage selectable on both comparators; configurable on either positive or negative comparator input channels. * Voltage ladder source voltage is selectable from an external pin or an internal 3.3 V voltage rail if external power source is not available. * Voltage ladder can be separately powered down for applications only requiring the comparator function. * Relaxation oscillator circuitry output for a feedback 555-style timer application. * Common interrupt connected to NVIC. * Comparator outputs selectable as synchronous or asynchronous. LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 21 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller * Comparator outputs connect to two timers, allowing for the recording of comparison event time stamps. 7.15 General purpose external event counter/timers The LPC122x includes two 32-bit counter/timers and two 16-bit counter/timers. The counter/timer is designed to count cycles of the system derived clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. Each counter/timer also includes up to four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.15.1 Features * A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler. * Counter or timer operation. * Up to four capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also generate an interrupt. * Four match registers per timer that allow: - Continuous operation with optional interrupt generation on match. - Stop timer on match with optional interrupt generation. - Reset timer on match with optional interrupt generation. * Up to four external outputs corresponding to match registers, with the following capabilities: - Set LOW on match. - Set HIGH on match. - Toggle on match. - Do nothing on match. * The timer and prescaler may be configured to be cleared on a designated capture event. This feature permits easy pulse width measurement by clearing the timer on the leading edge of an input pulse and capturing the timer value on the trailing edge. * Supports timed DMA requests. 7.16 Windowed WatchDog timer (WWDT) The purpose of the watchdog is to reset the microcontroller within a windowed amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to `feed' (or reload) the watchdog within a predetermined amount of time. 7.16.1 Features * * * * * * LPC122X Internally resets chip if not periodically reloaded. Debug mode. Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. Safe operation: can be locked by software to be always on. Flag to indicate watchdog reset. Programmable 24-bit timer with internal prescaler. All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 22 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller * Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 224 4) in multiples of Tcy(WDCLK) 4. * The Watchdog Clock (WDCLK) source can be selected from the Internal RC oscillator (IRC) or the Watchdog oscillator. This gives a wide range of potential timing choices of Watchdog operation under different power reduction conditions. It also provides the ability to run the WDT from an entirely internal source that is not dependent on an external crystal and its associated components and wiring for increased reliability. 7.17 Real-time clock (RTC) The RTC provides a basic alarm function or can be used as a long time base counter. The RTC generates an interrupt after counting for a programmed number of cycles of the RTC clock input. 7.17.1 Features * Uses dedicated 32 kHz ultra low-power oscillator. * Selectable clock inputs: RTC oscillator (1 Hz, delayed 1 Hz, or 1 kHz clock) or main clock with programmable clock divider. * * * * 32-bit counter. Programmable 32-bit match/compare register. Software maskable interrupt when counter and compare registers are identical. Generates wake-up from Deep-sleep and Deep power-down modes. 7.18 Clocking and power control 7.18.1 Crystal oscillators The LPC122x include four independent oscillators. These are the system oscillator, the Internal RC oscillator (IRC), the RTC 32 kHz oscillator (for the RTC only), and the Watchdog oscillator. Except for the RTC oscillator, each oscillator can be used for more than one purpose as required in a particular application. Following reset, the LPC122x will operate from the Internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency. See Figure 5 for an overview of the LPC122x clock generation. LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 23 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller main clock CLOCK DIVIDER system clock 31 AHB clock 0 (system) AHB clocks 1 to 31 (memories and peripherals) SYSAHBCLKCTRL[1:31] (AHB clock enable) 3 CLOCK DIVIDER peripheral clocks (SSP, UART0, UART1) 7 CLOCK DIVIDER peripheral clocks (IOCONFIG glitch filter) CLOCK DIVIDER IRC oscillator RTC oscillator 1 Hz clock RTC oscillator 1 Hz delayed clock RTC oscillator 1 kHz clock RTC watchdog oscillator MAINCLKSEL (main clock select) IRC oscillator system oscillator SYSTEM PLL IRC oscillator system oscillator watchdog oscillator RTCOSCCTRL CLOCK DIVIDER CLKOUT pin SYSPLLCLKSEL CLKOUTUEN (CLKOUT clock update enable) IRC oscillator WWDT watchdog oscillator WDCLKSEL (WWDT clock select) 002aaf271 Fig 5. LPC122x clocking generation block diagram 7.18.1.1 Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed to 1 % accuracy over the entire voltage and temperature range. Upon power-up or any chip reset, the LPC122x use the IRC as the clock source. Software may later switch to one of the other available clock sources. 7.18.1.2 System oscillator The system oscillator can be used as the clock source for the CPU, with or without using the PLL. LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 24 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the system PLL. The ARM processor clock frequency is referred to as CCLK elsewhere in this document. 7.18.1.3 Watchdog oscillator The watchdog oscillator can be used as a clock source that directly drives the CPU, the watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is programmable between 7.8 kHz and 1.7 MHz. The frequency spread over processing and temperature is 40 %. 7.18.2 System PLL The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. The PLL output frequency must be lower than 100 MHz. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source. The PLL settling time is 100 s. 7.18.3 Clock output The LPC122x features a clock output function that routes the IRC oscillator, the system oscillator, the watchdog oscillator, or the main clock to an output pin. 7.18.4 Wake-up process The LPC122x begin operation at power-up and when awakened from Deep power-down mode by using the 12 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source. 7.18.5 Power control The LPC122x support a variety of power control features. There are three special modes of processor power reduction: Sleep mode, Deep-sleep mode, and Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, a register is provided for shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Selected peripherals have their own clock divider which provides even better power control. 7.18.5.1 Sleep mode When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep mode does not need any special sequence but re-enabling the clock to the ARM core. LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 25 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller In Sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 7.18.5.2 Deep-sleep mode In Deep-sleep mode, the chip is in Sleep mode, and in addition all analog blocks are shut down. As an exception, the user has the option to keep the watchdog oscillator and the BOD circuit running for self-timed wake-up and BOD protection. Deep-sleep mode allows for additional power savings. The GPIO pins PIO0_0 to PIO0_11 (up to 12 pins total) and the RTC match interrupt can serve as a wake-up input to the start logic to wake up the chip from Deep-sleep mode. Unless the watchdog oscillator is selected to run in Deep-sleep mode, the clock source should be switched to IRC before entering Deep-sleep mode, because the IRC can be switched on and off glitch-free. 7.18.5.3 Deep power-down mode In Deep power-down mode, power is shut off to the entire chip with the exception of the Real Time Clock, the four general-purpose registers, and the WAKEUP pin. The LPC122x can wake up from Deep power-down mode via the WAKEUP pin or the RTC match interrupt. When entering Deep power-down mode, an external pull-up resistor is required on the WAKEUP pin to hold it HIGH. The RESET pin must also be held HIGH to prevent it from floating while in Deep power-down mode. 7.19 System control 7.19.1 Start logic The start logic connects external pins to corresponding interrupts in the NVIC. Each pin shown in Table 3 as input to the start logic has an individual interrupt in the NVIC interrupt vector table. The start logic pins can serve as external interrupt pins when the chip is running. In addition, an input signal on the start logic pins can wake up the chip from Deep-sleep mode when all clocks are shut down. The start logic must be configured in the system configuration block and in the NVIC before being used. 7.19.2 Reset Reset has four sources on the LPC122x: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage attains a usable level, starts the IRC and initializes the flash controller. When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the boot block. At that point, all of the processor and peripheral registers have been initialized to predetermined values. LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 26 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller An external pull-up resistor is required on the RESET pin if Deep power-down mode is used. 7.19.3 Brownout detection The LPC122x includes four levels for monitoring the voltage on the VDD(3V3) pin. If this voltage falls below one of the four selected levels, the BOD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. An additional threshold level can be selected to cause a forced reset of the chip. 7.19.4 Code security (Code Read Protection - CRP) This feature of the LPC122x allows user to enable different levels of security in the system so that access to the on-chip flash and use of the SWD and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP. There are three levels of Code Read Protection: 1. CRP1 disables access to chip via the SWD and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased. 2. CRP2 disables access to chip via the SWD and only allows full flash erase and update using a reduced set of the ISP commands. 3. Running an application with level CRP3 selected fully disables any access to chip via the SWD pins and the ISP. This mode effectively disables ISP override using PIO0_12 pin, too. It is up to the user's application to provide (if needed) flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via UART0. CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. In addition to the three CRP levels, sampling of pin PIO0_12 for valid user code can be disabled. 7.19.5 APB interface The APB peripherals are located on one APB bus. 7.19.6 AHB-Lite The AHB-Lite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main static RAM, and the Boot ROM. 7.19.7 External interrupt inputs All GPIO pins can be level or edge sensitive interrupt inputs. LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 27 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller 7.20 Emulation and debugging Debug functions are integrated into the ARM Cortex-M0. Serial wire debug is supported. 7.21 Integer division routines The LPC122x contain performance-optimized integer division routines with support for up to 32-bit width in the numerator and denominator. Routines for signed and unsigned division and division with remainder are available. The integer division routines are ROM-based to reduce code-size. LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 28 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol VDD(3V3) VDD(IO) VI Parameter supply voltage (3.3 V) input/output supply voltage input voltage on all digital pins on pins PIO0_10 and PIO0_11 (I2C-bus pins) IDD ISS Ilatch supply current ground current I/O latch-up current per supply pin per ground pin (0.5VDD) < VI < (1.5VDD); Tj < 125 C Tstg Ptot(pack) storage temperature total power dissipation (per package) based on package heat transfer, not device power consumption human body model; all pins [5] [4] [3] [3] [2] Conditions Min 3.0 3.0 0.5 Max 3.6 3.6 +3.6 Unit V V V V - 100 100 100 mA mA mA 65 - +150 1.5 C W VESD electrostatic discharge voltage 8000 +8000 V [1] The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. [2] [3] [4] [5] Including voltage on outputs in 3-state mode. The peak current is limited to 25 times the corresponding maximum current. Dependent on package type. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 29 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller 9. Thermal characteristics 9.1 Thermal characteristics The average chip junction temperature, Tj (C), can be calculated using the following equation: T j = T amb + P D R th j - a (1) * Tamb = ambient temperature (C), * Rth(j-a) = the package junction-to-ambient thermal resistance (C/W) * PD = sum of internal and I/O power dissipation The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of the I/O pins is often small and many times can be negligible. However it can be significant in some applications. Table 6. Thermal characteristics VDD = 3.0 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified. Symbol Rth(j-a) Parameter thermal resistance from junction to ambient Conditions JEDEC test board; no air flow LQFP64 package LQFP48 package Rth(j-c) thermal resistance from junction to case JEDEC test board LQFP64 package LQFP48 package Tj(max) maximum junction temperature 19 36 150 C/W C/W C Min 61 86 C/W C/W Typ Max Unit LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 30 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller 10. Static characteristics Table 7. Static characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol VDD(IO) VDD(3V3) IDD Parameter input/output supply voltage supply voltage (3.3 V) supply current Active mode; VDD(3V3) = 3.3 V; Tamb = 25 C; code Conditions on pin VDD(IO) Min 3.0 3.0 Typ[1] 3.3 3.3 Max 3.6 3.6 Unit V V while(1){} executed from flash all peripherals disabled: CCLK = 12 MHz CCLK = 24 MHz CCLK = 33 MHz all peripherals enabled: CCLK = 12 MHz CCLK = 24 MHz CCLK = 33 MHz Sleep mode; VDD(3V3) = 3.3 V; Tamb = 25 C; all peripherals disabled CCLK = 12 MHz CCLK = 24 MHz CCLK = 33 MHz Deep-sleep mode; VDD(3V3) = 3.3 V; Tamb = 25 C Deep power-down mode; VDD(3V3) = 3.3 V; Tamb = 25 C Standard port pins, RESET IIL IIH IOZ VI VO VIH LOW-level input current HIGH-level input current OFF-state output current input voltage output voltage HIGH-level input voltage VI = 0 V; VI = VDD(IO); VO = 0 V; VO = VDD(IO); pin configured to provide a digital function output active [2][3][4] - 3.1 5.6 8.1 5.3 9.5 13.7 - mA mA mA mA mA mA - 2.0 3.5 5.0 23.5 - mA mA mA A - 680 - nA 0 0 0.7VDD(IO) - 1 1 1 VDD(IO) VDD(IO) - A A A V V V LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 31 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller Table 7. Static characteristics ...continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol VIL Vhys VOH VOL IOH Parameter LOW-level input voltage hysteresis voltage HIGH-level output voltage LOW-level output voltage HIGH-level output current IOH = 4 mA IOL = 4 mA VOH = 2.4 V Normal-drive pins; low mode Normal-drive pins; high mode High-drive pins; low mode High-drive pins; high mode IOL LOW-level output current VOL = 0.4 V Normal-drive pins; low mode Normal-drive pins; high mode High-drive pins; low mode High-drive pins; high mode IOHS HIGH-level short-circuit output current LOW-level short-circuit output current pull-up current pins (PIO0_10 and PIO0_11) HIGH-level input voltage LOW-level input voltage hysteresis voltage LOW-level output voltage input leakage current capacitance for each I/O pin IOLS = 20 mA VI = VDD(IO) VI = 5 V Ci on pins PIO0_10 and PIO0_11 [8] [5] [5] [5] Conditions Min 2.4 3.9 Typ[1] 0.4 7.8 Max 0.3VDD(IO) 0.4 12.9 Unit V V V V mA 7.7 17.4 23.1 3.4 15.6 35.1 46.8 5.4 25.8 58.1 77.5 7.4 mA mA mA mA [6] [6] [5] 6.7 13.4 20.1 - 10.7 21.5 32.2 - 14.7 29.4 44.1 45 mA mA mA mA [6] [6] VOH = 0 V [7] IOLS VOL = VDDA [7] - - 50 mA Ipu I2C-bus VIH VIL Vhys VOL ILI VI = 0 V 50 0.7VDD(IO) - 80 - 100 0.3VDD(IO) A V V V V A A pF 0.05VDD(IO) 2 10 0.4 4 22 8 LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 32 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller Table 7. Static characteristics ...continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Oscillator pins Vi(xtal) Vo(xtal) [1] [2] [3] [4] [5] [6] [7] [8] Parameter crystal input voltage crystal output voltage Conditions Min 0 0 Typ[1] 1.8 1.8 Max 1.95 1.95 Unit V V Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. Including voltage on outputs in 3-state mode. VDD(3V3) and VDD(IO) supply voltages must be present. 3-state outputs go into 3-state mode when VDD(IO) is grounded. Normal-drive output mode applies to all GPIO pins except pins PIO0_12, PIO0_27, PIO0_28, PIO0_29. High-drive output mode available on pins PIO0_12, PIO0_27, PIO0_28, PIO0_29. Allowed as long as the current limit does not exceed the maximum current allowed by the device. To VSS. LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 33 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller 10.1 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code is executed. Measured on a typical sample at Tamb = 25 C. Unless noted otherwise, the system oscillator and PLL are running in both measurements. The supply currents are shown for system clock frequencies of Table 8. Peripheral Power consumption for individual analog and digital blocks Typical supply current in mA n/a IRC System oscillator at 12 MHz Watchdog oscillator at 500 kHz/2 BOD Main PLL CRC 16-bit timer 0 (CT16B0) 16-bit timer 1 (CT16B1) 32-bit timer 0 (CT32B0) 32-bit timer 1 (CT32B1) SSP/SPI UART0 UART1 ADC WWDT DMA RTC Comparator SysTick timer 10.2 Power consumption Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see LPC122x user manual): * LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 34 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller X X (X) X 001aab173 X X X X X X X X (X) X X X Conditions: Tamb = 25 C; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = Fig 6. Active mode: Typical supply current IDD versus supply voltage VDD(3V3) for different system clock frequencies 16 IDD (mA) 12 24 MHz 8 002aag023 33 MHz 12 MHz 4 4 MHz 1 MHz 0 -40 -15 10 35 60 85 temperature (C) Conditions: VDD(3V3) = 3.3 V; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = Fig 7. Active mode: Typical supply current IDD versus temperature for different system clock frequencies (peripherals disabled) LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 35 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller 16 33 MHz IDD (mA) 12 24 MHz 002aag024 8 12 MHz 4 4 MHz 1 MHz 0 -40 -15 10 35 60 85 temperature (C) Conditions: VDD(3V3) = 3.3 V; active mode entered executing code while(1){} from flash; all peripherals enabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = Fig 8. Active mode: Typical supply current IDD versus temperature for different system clock frequencies (peripherals enabled) X X (X) X 001aab173 X X X X X X X X (X) X X X Conditions: VDD(3V3) = 3.3 V; sleep mode entered from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = Fig 9. Sleep mode: Typical supply current IDD versus temperature for different system clock frequencies LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 36 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller 35 IDD (A) 30 VDD(3V3) = 3.6 V 3.3 V 3.0 V 25 002aag021 20 15 -40 -15 10 35 60 85 temperature (C) Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register (PDSLEEPCFG = Fig 10. Deep-sleep mode: Typical supply current IDD versus temperature for different supply voltages VDD(3V3) X X (X) X 001aab173 X X X X X X X X (X) X X X Fig 11. Deep power-down mode: Typical supply current IDD versus temperature for different supply voltages VDD(3V3) LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 37 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller 10.3 Electrical pin characteristics X X (X) X 001aab173 X X X X X X X X (X) X X X Conditions: VDD(IO) = 3.3 V. Fig 12. High-drive output: Typical HIGH-level output voltage VOH versus HIGH-level output current IOH X X (X) X 001aab173 X X X X X X X X (X) X X X Conditions: VDD(IO) = 3.3 V. Fig 13. I2C-bus pins (high current sink): Typical LOW-level output current IOL versus LOW-level output voltage VOL LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 38 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller X X (X) X 001aab173 X X X X X X X X (X) X X X Conditions: VDD(IO) = 3.3 V. Fig 14. Typical LOW-level output current IOL versus LOW-level output voltage VOL X X (X) X 001aab173 X X X X X X X X (X) X X X Conditions: VDD(IO) = 3.3 V. Fig 15. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 39 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller X X (X) X 001aab173 X X X X X X X X (X) X X X Conditions: VDD(IO) = 3.3 V. Fig 16. Typical pull-up current Ipu versus input voltage VI LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 40 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller 10.4 ADC characteristics Table 9. ADC static characteristics Tamb = 40 C to +85 C unless otherwise specified; ADC frequency 9 MHz, VDD(3V3) = 3.0 V to 3.6 V. Symbol VIA Cia ED EL(adj) EO EG ET fc(ADC) [1] [2] [3] [4] [5] [6] [7] [8] Parameter analog input voltage analog input capacitance differential linearity error integral non-linearity offset error gain error absolute error ADC conversion frequency Conditions Min 0 [2][3][4] [2][5] [2][6] [2][7] [2][8] Typ[1] - Max VDD(3V3) 1 1 2.5 1 3 3 257 Unit V pF LSB LSB LSB LSB LSB kHz - Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. Conditions: VSS = 0 V, VDD(3V3) = 3.3 V. The ADC is monotonic, there are no missing codes. The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 17. The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 17. The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 17. The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 17. The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. See Figure 17. LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 41 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller offset error EO 1023 gain error EG 1022 1021 1020 1019 1018 (2) 7 code out 6 (1) 5 (5) 4 (4) 3 (3) 2 1 1 LSB (ideal) 1018 1019 1020 1021 1022 1023 1024 0 1 offset error EO 2 3 4 5 6 7 VIA (LSBideal) 1 LSB = VDD(3V3) - VSS 1024 002aae787 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve. Fig 17. ADC characteristics LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 42 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller 10.5 BOD static characteristics Table 10. BOD static characteristics[1] Tamb = 25 C. Symbol Vth Parameter threshold voltage Conditions interrupt level 1 assertion de-assertion interrupt level 2 assertion de-assertion interrupt level 3 assertion de-assertion reset level 1 assertion de-assertion reset level 2 assertion de-assertion reset level 3 assertion de-assertion [1] Min - Typ 2.25 2.39 2.54 2.67 2.83 2.93 2.04 2.18 2.34 2.47 2.62 2.76 Max - Unit V V V V V V V V V V V V Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC122x user manual. LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 43 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller 11. Dynamic characteristics 11.1 Flash memory Table 11. Dynamic characteristic: flash memory Tamb = 40 C to +85 C; VDD(3V3) over specified ranges. Symbol ter Parameter erase time Conditions for one page (512 byte) for one sector (4 kB) for all sectors; mass erase tprog programming time one word (4 bytes) four sequential words 128 bytes (one row of 32 words) Nendu tret [1] [2] [1] [1] [1] Min 20000 10 Max 20 162 20 49 194 765 - Unit ms ms ms s s s cycles years [1] [1] [1] endurance retention time [2] Erase and programming times are valid over the lifetime of the device (minimum 20000 cycles). Number of program/erase cycles. 11.2 External clock Table 12. Dynamic characteristic: external clock Tamb = 40 C to +85 C; VDD(3V3) over specified ranges.[1] Symbol fosc Tcy(clk) tCHCX tCLCX tCLCH tCHCL [1] [2] Parameter oscillator frequency clock cycle time clock HIGH time clock LOW time clock rise time clock fall time Conditions Min 1 40 Tcy(clk) 0.4 Tcy(clk) 0.4 - Typ[2] - Max 25 1000 5 5 Unit MHz ns ns ns ns ns Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. tCHCL tCLCX Tcy(clk) tCHCX tCLCH 002aaa907 Fig 18. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 44 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller 11.3 Internal oscillators Table 13. Dynamic characteristic: internal oscillators Tamb = 40 C to +85 C; VDD(3V3) over specified ranges.[1] Symbol fosc(RC) [1] [2] Parameter internal RC oscillator frequency Conditions - Min 11.88 Typ[2] 12 Max 12.12 Unit MHz Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at nominal supply voltages. 12.15 12 MHz + 1% fosc(RC) (MHz) 12.05 VDD = 3.6 V 3.3 V 3.0 V 002aag020 11.95 12 MHz - 1% 11.85 -40 -15 10 35 60 85 temperature (C) Fig 19. Internal RC oscillator frequency versus temperature Table 14. fosc(int) Dynamic characteristics: Watchdog oscillator Conditions [2][3] Symbol Parameter Min - Typ[1] 7.8 1700 Max - Unit kHz kHz internal oscillator DIVSEL = 0x1F, FREQSEL = 0x1 frequency in the WDTOSCCTRL register; DIVSEL = 0x00, FREQSEL = 0xF in the WDTOSCCTRL register [2][3] [1] [2] [3] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. The typical frequency spread over processing and temperature (Tamb = 40 C to +85 C) is 40 %. See the LPC122x user manual. 11.4 I2C-bus Table 15. Dynamic characteristic: I2C-bus pins Tamb = 40 C to +85 C.[1] Symbol fSCL Parameter SCL clock frequency Conditions Standard-mode Fast-mode Fast-mode Plus Min 0 0 0 Max 100 400 1 Unit kHz kHz MHz LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 45 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller Table 15. Dynamic characteristic: I2C-bus pins Tamb = 40 C to +85 C.[1] Symbol tf Parameter fall time [3][4][5][6] Conditions of both SDA and SCL signals Standard-mode Fast-mode Fast-mode Plus Min - Max 300 Unit ns 20 + 0.1 Cb 4.7 1.3 0.5 4.0 0.6 0.26 0 0 0 250 100 50 300 120 - ns ns s s s s s s s s s ns ns ns tLOW LOW period of the SCL clock Standard-mode Fast-mode Fast-mode Plus tHIGH HIGH period of the SCL clock Standard-mode Fast-mode Fast-mode Plus tHD;DAT data hold time [2][3][7] Standard-mode Fast-mode Fast-mode Plus tSU;DAT data set-up time [8][9] Standard-mode Fast-mode Fast-mode Plus [1] [2] [3] [4] [5] Parameters are valid over operating temperature range unless otherwise specified. tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge. A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall times are allowed. The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. [6] [7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing. The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the acknowledge. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time. [8] [9] LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 46 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller tf SDA 70 % 30 % tf 70 % 30 % 70 % 30 % tHD;DAT tSU;DAT tVD;DAT tHIGH SCL 70 % 30 % 70 % 30 % tLOW 70 % 30 % S 1 / fSCL 002aaf425 Fig 20. I2C-bus pins clock timing LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 47 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller 11.5 SSP/SPI interface Table 16. Dynamic characteristics: SSP pins in SPI mode Tamb = 25 C. Symbol Tcy(clk) Parameter clock cycle time Conditions when only transmitting when only receiving SSP master tDS tDH tv(Q) th(Q) SSP slave tDS tDH tv(Q) th(Q) [1] [1] Min Max - Unit ns data set-up time data hold time data output valid time data output hold time data set-up time data hold time data output valid time data output hold time in SPI mode in SPI mode in SPI mode in SPI mode in SPI mode in SPI mode in SPI mode in SPI mode [2] [2] [2] [2] 15 0 0 0 3 Tcy(PCLK) + 4 - 10 3 Tcy(PCLK) + 11 2 Tcy(PCLK) + 5 ns ns ns ns ns ns ns ns [3][4] [3][4] [3][4] [3][4] Tcy(clk) = (SSPCLKDIV (1 + SCR) CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the main clock frequency fmain, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0 register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register). Tamb = 40 C to 85 C; VDD(3V3) = 3.0 V to 3.6 V; VDD(IO) = 3.0 V to 3.6 V. Tcy(clk) = 12 Tcy(PCLK). Tamb = 25 C; VDD(3V3) = 3.3 V; VDD(IO) = 3.3 V. [2] [3] [4] LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 48 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller Tcy(clk) tclk(H) tclk(L) SCK (CPOL = 0) SCK (CPOL = 1) tv(Q) MOSI DATA VALID DATA VALID tDS MISO DATA VALID tDH DATA VALID CPHA = 1 th(Q) tv(Q) MOSI DATA VALID DATA VALID tDS MISO DATA VALID tDH DATA VALID th(Q) CPHA = 0 002aae829 Fig 21. SSP master timing in SPI mode LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 49 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller Tcy(clk) tclk(H) tclk(L) SCK (CPOL = 0) SCK (CPOL = 1) tDS MOSI DATA VALID tv(Q) MISO DATA VALID DATA VALID tDH DATA VALID th(Q) CPHA = 1 tDS MOSI DATA VALID tv(Q) MISO DATA VALID tDH DATA VALID th(Q) DATA VALID CPHA = 0 002aae830 Fig 22. SSP slave timing in SPI mode LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 50 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller 12. Application information 12.1 XTAL input The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a clock in slave mode, it is recommended that the input be coupled through a capacitor with Ci = 100 pF. To limit the input voltage to the specified range, choose an additional capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave mode, a minimum of 200 mV(RMS) is needed. LPC1xxx XTALIN Ci 100 pF Cg 002aae788 Fig 23. Slave mode operation of the on-chip oscillator 12.2 XTAL Printed Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors Cx1,Cx2, and Cx3 in case of third overtone crystal usage have a common ground plane. The external components must also be connected to the ground plain. Loops must be made as small as possible in order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller accordingly to the increase in parasitics of the PCB layout. LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 51 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller 12.3 ElectroMagnetic Compatibility (EMC) Radiated emission measurements according to the IEC61967-2 standard using the TEM-cell method are shown for the LPC1227FBD64/301 in Table 17. ElectroMagnetic Compatibility (EMC) for part LPC1227FBD64/301 (TEM-cell method) VDD = 3.3 V; Tamb = 25 C. Parameter Frequency band System clock = 12 MHz Input clock: IRC (12 MHz) maximum peak level 150 kHz - 30 MHz 30 MHz - 150 MHz 150 MHz - 1 GHz IEC level[1] 150 kHz - 30 MHz 30 MHz - 150 MHz 150 MHz - 1 GHz IEC level[1] [1] Table 17. Unit 24 MHz Input clock: crystal oscillator (12 MHz) maximum peak level - IEC levels refer to Appendix D in the IEC61967-2 Specification. LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 52 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller 13. Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2 c y X A 48 49 33 32 ZE e E HE wM bp 64 1 pin 1 index 16 ZD bp D HD wM B vM B vM A 17 detail X L Lp A A2 A1 (A 3) e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 1.45 1.05 1.45 1.05 7o o 0 12.15 12.15 11.85 11.85 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT314-2 REFERENCES IEC 136E10 JEDEC MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 03-02-25 Fig 24. Package outline SOT314-2 (LQFP64) LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 53 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 37 25 24 ZE A e E HE A A2 A1 (A 3) Lp L detail X wM pin 1 index 48 1 12 ZD bp D HD wM B vM B vM A 13 bp e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.5 HD 9.15 8.85 HE 9.15 8.85 L 1 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 0.95 0.55 0.95 0.55 7o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT313-2 REFERENCES IEC 136E05 JEDEC MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 03-02-25 Fig 25. Package outline SOT313-2 (LQFP48) LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 54 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller 14. Abbreviations Table 18. Acronym ADC AHB APB BOD CCITT CRC DMA FIFO GPIO I/O IrDA IRC JEDEC PLL SPI SSI SSP UART Abbreviations Description Analog-to-Digital-Converter Advanced High-performance Bus Advanced Peripheral Bus BrownOut Detection Comite Consultatif International Telephonique et Telegraphique Cyclic Redundancy Check Direct Memory Access First-In-First-Out General Purpose Input/Output Input/Output Infrared Data Association Internal Resistor-Capacitor Joint Electron Devices Engineering Council Phase-Locked Loop Serial Peripheral Interface Serial Synchronous Interface Synchronous Serial Port Universal Asynchronous Receiver/Transmitter LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 55 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller 15. Revision history Table 19. Revision history Release date 20110221 Data sheet status Objective data sheet Change notice Supersedes LPC122X v.1 Document ID LPC122X v.1.1 Modifications: LPC122X v.1 * * Section 1 "General description": Updated text. Section 2 "Features and benefits": Updated text. Objective data sheet - 20110214 LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 56 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 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NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. (c) NXP B.V. 2011. All rights reserved. 16.3 Disclaimers Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or LPC122X All information provided in this document is subject to legal disclaimers. Objective data sheet Rev. 1.1 -- 21 February 2011 57 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications. Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 58 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller 18. Contents General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional description . . . . . . . . . . . . . . . . . . 16 ARM Cortex-M0 processor . . . . . . . . . . . . . . . 16 System tick timer . . . . . . . . . . . . . . . . . . . . . . 16 On-chip flash program memory . . . . . . . . . . . 16 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 16 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 16 Nested Vectored Interrupt Controller (NVIC) . 17 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 18 IOCONFIG block . . . . . . . . . . . . . . . . . . . . . . 18 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Micro DMA controller . . . . . . . . . . . . . . . . . . . 18 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 CRC engine . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Fast general purpose parallel I/O . . . . . . . . . . 19 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 UARTs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SSP/SPI serial I/O controller . . . . . . . . . . . . . 20 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 I2C-bus serial I/O controller . . . . . . . . . . . . . . 20 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Comparator block . . . . . . . . . . . . . . . . . . . . . . 21 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 General purpose external event counter/timers . . 22 7.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.16 Windowed WatchDog timer (WWDT) . . . . . . . 22 7.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.17 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . 23 7.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.18 Clocking and power control . . . . . . . . . . . . . . 23 7.18.1 Crystal oscillators . . . . . . . . . . . . . . . . . . . . . . 23 7.18.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 24 7.18.1.2 System oscillator . . . . . . . . . . . . . . . . . . . . . . 24 1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 7.1.1 7.2 7.3 7.4 7.5 7.5.1 7.5.2 7.6 7.6.1 7.7 7.7.1 7.8 7.8.1 7.9 7.9.1 7.10 7.10.1 7.11 7.11.1 7.12 7.12.1 7.13 7.13.1 7.14 7.14.1 7.15 7.18.1.3 Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 7.18.2 System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 7.18.3 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 7.18.4 Wake-up process . . . . . . . . . . . . . . . . . . . . . . 7.18.5 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 7.18.5.1 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 7.18.5.2 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 7.18.5.3 Deep power-down mode . . . . . . . . . . . . . . . . 7.19 System control . . . . . . . . . . . . . . . . . . . . . . . . 7.19.1 Start logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.19.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.19.3 Brownout detection . . . . . . . . . . . . . . . . . . . . 7.19.4 Code security (Code Read Protection - CRP) 7.19.5 APB interface . . . . . . . . . . . . . . . . . . . . . . . . . 7.19.6 AHB-Lite . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.19.7 External interrupt inputs . . . . . . . . . . . . . . . . . 7.20 Emulation and debugging . . . . . . . . . . . . . . . 7.21 Integer division routines . . . . . . . . . . . . . . . . . 8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 9 Thermal characteristics . . . . . . . . . . . . . . . . . 9.1 Thermal characteristics . . . . . . . . . . . . . . . . . 10 Static characteristics . . . . . . . . . . . . . . . . . . . 10.1 Peripheral power consumption . . . . . . . . . . . 10.2 Power consumption . . . . . . . . . . . . . . . . . . . 10.3 Electrical pin characteristics. . . . . . . . . . . . . . 10.4 ADC characteristics . . . . . . . . . . . . . . . . . . . . 10.5 BOD static characteristics . . . . . . . . . . . . . . . 11 Dynamic characteristics. . . . . . . . . . . . . . . . . 11.1 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 11.2 External clock. . . . . . . . . . . . . . . . . . . . . . . . . 11.3 Internal oscillators . . . . . . . . . . . . . . . . . . . . . 11.4 I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.5 SSP/SPI interface . . . . . . . . . . . . . . . . . . . . . 12 Application information . . . . . . . . . . . . . . . . . 12.1 XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 XTAL Printed Circuit Board (PCB) layout guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3 ElectroMagnetic Compatibility (EMC) . . . . . . 13 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information . . . . . . . . . . . . . . . . . . . . . . 16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 16.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 25 25 25 25 25 25 26 26 26 26 26 27 27 27 27 27 28 28 29 30 30 31 34 34 38 41 43 44 44 44 45 45 48 51 51 51 52 53 55 56 57 57 57 57 58 continued >> LPC122X All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1.1 -- 21 February 2011 59 of 60 NXP Semiconductors LPC122x 32-bit ARM Cortex-M0 microcontroller 17 18 Contact information. . . . . . . . . . . . . . . . . . . . . 58 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 21 February 2011 Document identifier: LPC122X |
Price & Availability of LPC1224FBD48101
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